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700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
ICS8735-21 Features
* * * * * * * * * * * * *
One differential 3.3V LVPECL output pair One differential feedback output pair Differential CLK/nCLK input pair CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output frequency range: 31.25MHz to 700MHz Input frequency range: 31.25MHz to 700MHz VCO range: 250MHz to 700MHz External feedback for "zero delay" clock regeneration with configurable frequencies Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Cycle-to-cycle jitter: 25ps (maximum) Static phase offset: 50ps 100ps Full 3.3V supply voltage 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
CLK nCLK MR VCC nFB_IN FB_IN SEL2 VEE nQFB QFB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc SEL1 SEL0 VCC PLL_SEL VCCA SEL3 VCCO Q nQ
General Description
The ICS8735-21 is a highly versatile 1:1 DifferentialICS to-3.3V LVPECL clock generator and a member of HiPerClockSTM the HiPerClockSTMfamily of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The ICS8735-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
Pin Assignments
Block Diagram
PLL_SEL Pullup /1, /2, /4, /8, /16, /32, /64 CLK Pulldown nCLK Pullup 0 Q nQ
1
QFB nQFB
ICS8735-21 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View
PLL_SEL SEL3 VCCA VCC
VEE
PLL
nc
nc
FB_IN Pulldown nFB_IN Pullup
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
32 31 30 29 28 27 26 25 SEL0 SEL1 nc nc 1 2 24 VCCO nc Q nQ QFB nQFB nc VCCO
SEL0 Pulldown SEL1 Pulldown SEL2 Pulldown SEL3 Pulldown MR Pulldown
CLK nCLK nc MR
ICS8735-21 23 32-Lead VFQFN 3 22 5mm x 5mm x 0.925mm 4 21 package body 5 20 K Package 6 19 Top View
7 8 9
VCC
nc
18 17 10 11 12 13 14 15 16
VEE nc nc nFB_IN FB_IN SEL2 nc
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Table 1. Pin Descriptions
Name CLK nCLK nFB_IN FB_IN Input Input Input Input Type Pulldown Pullup Pullup Pulldown Description Non-inverting differential clock input. Inverting differential clock input. Inverting differential feedback input to phase detector for regenerating clocks with "zero delay." Non-inverted differential feedback input to phase detector for regenerating clocks with "zero delay." Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inverted output nQ to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. PLL select. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential feedback output pair. LVPECL interface levels. Negative supply pin. Core supply pins. Analog supply pin. Output supply pin.
MR SEL0, SEL1, SEL2, SEL3 PLL_SEL nQ, Q nQFB, QFB VEE VCC VCCA VCCO
Input
Pulldown
Input
Pulldown
Input Output Output Power Power Power Power
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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Function Tables
Table 3A. Control Input Function Table
Inputs Outputs PLL_SEL = 1 PLL Enable Mode Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 250 - 700 125 - 350 62.5 - 175 250 - 700 125 - 350 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 62.5 - 175 31.25 - 87.5 31.25 - 87.5 Q/nQ, QFB/nQFB /1 /1 /1 /1 /2 /2 /2 /4 /4 /8 x2 x2 x2 x4 x4 x8
SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
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Table 3B. PLL Bypass Function Table
Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Q/nQ, QFB/nQFB /4 /4 /4 /8 /8 /8 /16 /16 /32 /64 /2 /2 /4 /1 /2 /1
SEL3 0z 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, JA 20 Lead SOIC 32 Lead VFQFN Storage Temperature, TSTG Rating 4.6V -0.5V to VCC + 0.5V 50mA 100mA 46.2C/W (0 lfpm) 37.0C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 150 15 Units V V V mA mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage SEL[0:3], MR Input High Current PLL_SEL SEL[0:3], MR IIL Input Low Current PLL_SEL VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
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Table 4C. Differential DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Symbol IIH Parameter CLK, FB_IN Input High Current nCLK, nFB_IN CLK, FB_IN IIL Input Low Current nCLK, nFB_IN VPP VCMR Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 VEE + 0.5 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
Table 5. Input Frequency Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Symbol fIN Parameter Input Frequency CLK, nCLK PLL_SEL = 0 700 MHz Test Conditions PLL_SEL = 1 Minimum 31.25 Typical Maximum 700 Units MHz
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AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Parameter Symbol fMAX tPD tsk(o) tsk(O) tjit(cc) tjit() tL tR / tF odc Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 3 Static Phase Offset; NOTE 3, 4 Cycle-to-Cycle Jitter; NOTE 3, 5 Phase Jitter; NOTE 3, 5, 6 PLL Lock Time Output Rise/Fall Time; NOTE 7 Output Duty Cycle 20% to 80% @ 50MHz 300 47 PLL_SEL = 0V, f 700MHz PLL_SEL = 0V PLL_SEL = 3.3V -50 50 3.0 Test Conditions Minimum Typical Maximum 700 4.2 20 150 25 50 1 700 53 Units MHz ns ps ps ps ps ms ps %
NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 5: Characterized at VCO frequency of 622MHz. NOTE 6: Phase jitter is dependent on the input source used.
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Parameter Measurement Information
2V
VCC
VCC, VCCA, VCCO
Qx
SCOPE
nCLK
V
PP
Cross Points
V
CMR
CLK
LVPECL
nQx VEE
VEE
1.3V 0.165V
3.3V Output Load AC Test Circuit
Differential Input Level
nCLK CLK nFB_IN FB_IN
VOH VOL VOH VOL t(O)
nQx Qx
nQy Qy
tsk(o)
Phase Jitter and Static Phase Offset
Output Skew
nQ, nQFB Q, QFB
80% Clock Outputs
80% VSW I N G
tcycle n
tcycle n+1
20% tR tF
20%
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
Cycle-to-Cycle Jitter
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Output Rise/Fall Time
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Parameter Measurement Information, continued
nQ, nQFB nCLK Q, QFB
t PW
t
PERIOD
CLK nQ, nQFB
odc =
t PW t PERIOD
x 100%
Q, QFB
tPD
Output Duty Cycle/Pulse Width/Period
Propagation Delay
Application Information
Recommendations for Unused Input and Output Pins Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground.
FB_IN/nFB_IN Inputs
For applications not requiring the use of the differential input, both FB_IN and nFB_IN can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from FB_IN to ground.
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Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8735-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VCC .01F VCCA .01F 10F 10
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK
V_REF nCLK C1 0.1u
R2 1K
Figure 2. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V 3.3V 2.5V R3 120 Zo = 60 R4 120
2.5V
3.3V
*R3
33
Zo = 50 CLK Zo = 50 nCLK Zo = 60
CLK
nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver
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Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50 125 FOUT FIN Zo = 50 Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT FOUT
3.3V 125
FIN
RTT =
Zo = 50 84 84
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
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Schematic Example
Figure 5 shows a schematic example of the ICS8735-21. In this example, the input is driven by an HCSL driver. The zero delay buffer is configured to operate at 155.52MHz input and 77.75MHz output. The logic control pins are configured as follows: SEL [3:0] = 0101; PLL_SEL = 1 The decoupling capacitors should be physically located near the power pin. For ICS8735-21.
3.3V Zo = 50 Ohm
R7
VCC
(155.5 MHz)
VCC SEL2 R8 50 R9 50 R1 50 R2 50
U1 1 2 3 4 5 6 7 8 9 10 CLK nCLK MR VCCI nFB_IN FB_IN SEL2 VEE nQFB QFB ICS8735-21 nc SEL1 SEL0 VCCI PLL_SEL VCCA SEL3 VCCO Q nQ 20 19 18 17 16 15 14 13 12 11 SEL1 SEL0 VCC PLL_SEL VCCA SEL3 VCC
VCCA C11 0.01u 10 C16 10u
Zo = 50 Ohm HCSL
Zo = 50 Ohm + Zo = 50 Ohm
VCC
-
RU3 1K
RU4 1K
RU5 SP
RU6 1K
RU7 SP PLL_SEL SEL0 SEL1 SEL2 SEL3 R3 50
(77.75 MHz)
R4 50
LVPECL_input R5 50
Bypass capacitors located near the power pins VCC=3.3V SEL[3:0] = 0101, Divide by 2
(U1-4) VCC
C1 0.1uF
R6 50
(U1-17)
C2 0.1uF
(U1-13)
C3 0.1uF
RD3 SP
RD4 SP
RD5 1K
RD6 SP
RD7 1K
SP = Space (i.e. not intstalled)
Figure 5. ICS8735-21 LVPECL Buffer Schematic Example
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VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8735-21. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8735-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 150mA = 519.8mW Power (outputs)MAX = 30mW/Loaded output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX = (3.465V, with all outputs switching) = 519.8mW + 60mW = 579.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 83.2C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.580W * 83.2C/W = 118.3C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 7A. Thermal Resistance JA for 20 Lead SOIC, Forced Convection
JA vs. Air Flow Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 83.2C/W 46.2C/W 200 65.7C/W 39.7C/W 500 57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 7B. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 37.0C/W 1 32.4C/W 2.5 29.0C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL 50
VCCO - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCCO - 2V.
* * For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 8A. JA vs. Air Flow Table for a 20 Lead TSSOP
JA vs. Air Flow Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 83.2C/W 46.2C/W 200 65.7C/W 39.7C/W 500 57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 8B. JA vs. Air Flow Table for a 32 Lead VFQFN, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 37.0C/W 1 32.4C/W 2.5 29.0C/W
Transistor Count
The transistor count for ICS8735-21 is: 2969
Package Outline and Package Dimensions
Package Outline - M Suffix for 20 Lead SOIC Table 9A. Package Dimensions for 20 Lead SOIC
300 Millimeters All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 2.65 A1 0.10 A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e 1.27 Basic H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 0 7
Reference Document: JEDEC Publication 95, MS-013, MS-119
IDTTM / ICSTM 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
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ICS8735AM-21 REV. A JULY 31, 2008
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Package Outline - K Suffix for 32 Lead VFQFN
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L N 1 2 E2 (N -1)x e
E2 2
(Re f.) (Ref.)
(N -1)x e
(R ef.)
N &N Even
e (Ty p.) 2 If N & N
are Even
OR
To p View
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9B below.
Table 9B. Package Dimensions for 32 Lead VFQFN
JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220
IDTTM / ICSTM 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
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ICS8735AM-21 REV. A JULY 31, 2008
ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Ordering Information
Table 10. Ordering Information
Part/Order Number 8735AM-21 8735AM-21T 8735AM-21LF 8735AM-21LFT 8735AK-21LF 8735AK-21LFT Marking ICS8735AM-21 ICS8735AM-21 ICS8735AM-21LF ICS8735AM-21LF ICS8735A21L ICS8735A21L Package 20 Lead SOIC 20 Lead SOIC "Lead-Free" 20 Lead SOIC "Lead-Free" 20 Lead SOIC "Lead-Free" 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN Shipping Packaging Tube 1000 Tape & Reel Tube 1000 Tape & Reel Tray 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDTTM / ICSTM 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
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ICS8735AM-21 REV. A JULY 31, 2008
ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Contact Information:
www.IDT.com
Sales
800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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